이 웹사이트는 쿠키를 사용합니다. 이 사이트를 이용함으로써 귀하는 쿠키 사용에 동의하게 됩니다. 자세한 내용은 다음을 참조하세요. 개인 정보 정책.

이미지는 참고용입니다. 제품 사양 보기

W971GG6SB25I

Name: W971GG6SB25I
Rating: 4.5 (10 reviews)

DRAM Chip DDR2 SDRAM 1Gbit 64Mx16 1.8V 84-Pin WBGA

브랜드: WINBOND ELECTRONICS CORP

제조업체부품 #: W971GG6SB25I

패키지/케이스: 84-WBGA (8x12.5)

RoHS 상태:

재고상태: 6414 PC, 새로운 원본

상품 유형: DRAM

Warranty: 1 Year Ovaga Warranty - Find Out More

가격

*모든 가격은 USD 단위입니다.

In Stock:6414 PCS

- +

빠른 견적

다음에 대한 RFQ를 제출해 주십시오. W971GG6SB25I 또는 우리에게 이메일을 보내: 이메일: [email protected], 12시간 이내에 연락드리겠습니다.

수량^*

이메일^*

담당자 이름^*

회사

주목

SDRAM - DDR2 Memory IC 1Gbit Parallel 200 MHz 57.5 ns 84-WBGA (8x12.5)

Power Supply: VDD, VDDQ = 1.8 V ± 0.1 V
Double Data Rate architecture: two data transfers per clock cycle
CAS Latency: 3, 4, 5, 6 and 7
Burst Length: 4 and 8
Bi-directional, differential data strobes (DQS and DQS ) are transmitted / received with data
Edge-aligned with Read data and center-aligned with Write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CLK and CLK )
Data masks (DM) for write data
Commands entered on each positive CLK edge, data and data mask are referenced to
both edges of DQS
Posted CAS programmable additive latency supported to make command and
data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for
better signal quality
Auto-precharge operation for read and write bursts
Auto Refresh and Self Refresh modes
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)
Interface: SSTL_18
Packaged in WBGA 84 Ball (8x12.5 mm2), using Lead free materials with RoHS compliant

매개변수	값	매개변수	값
Rohs Code	Yes	Part Life Cycle Code	Obsolete
Ihs Manufacturer	WINBOND ELECTRONICS CORP	Package Description	TFBGA,
Reach Compliance Code	compliant	ECCN Code	EAR99
HTS Code	8542.32.00.32	Samacsys Manufacturer	Winbond
Access Mode	MULTI BANK PAGE BURST	Access Time-Max	0.4 ns
Additional Feature	AUTO/SELF REFRESH	JESD-30 Code	R-PBGA-B84
Length	12.5 mm	Memory Density	1073741824 bit
Memory IC Type	DDR DRAM	Memory Width	16
Number of Functions	1	Number of Ports	1
Number of Terminals	84	Number of Words	67108864 words
Number of Words Code	64000000	Operating Mode	SYNCHRONOUS
Organization	64MX16	Package Body Material	PLASTIC/EPOXY
Package Code	TFBGA	Package Shape	RECTANGULAR
Package Style	GRID ARRAY, THIN PROFILE, FINE PITCH	Peak Reflow Temperature (Cel)	NOT SPECIFIED
Seated Height-Max	1.2 mm	Self Refresh	YES
Supply Voltage-Max (Vsup)	1.9 V	Supply Voltage-Min (Vsup)	1.7 V
Supply Voltage-Nom (Vsup)	1.8 V	Surface Mount	YES
Technology	CMOS	Terminal Form	BALL
Terminal Pitch	0.8 mm	Terminal Position	BOTTOM
Time@Peak Reflow Temperature-Max (s)	NOT SPECIFIED

처리 시간: 배송비는 지역 및 국가에 따라 다릅니다.