Microchip KSZ8565RTXV-VAO

KSZ8565RTXV-VAO 일반적인 설명

In the realm of industrial Ethernet switches, the KSZ8565RTXV-VAO stands out as a versatile and dependable choice. Its rugged design and support for various industrial protocols make it an ideal option for demanding environments. Whether it's in a factory setting or a challenging outdoor location, this switch can handle the rigors of industrial applications with ease. With features like VLAN support and port-based access control, it offers the flexibility and security necessary for critical operations

특징

• Non-blocking wire-speed Ethernet switching fabric
• IEEE802.1AS (AVB) time synchronization support
• IEEE802.1Qav (AVB) credit based traffic shaper
• Time aware traffic scheduler with low latency cut-through mode
• IEEE1588v2 Precision Time Protocol support
• Time-stamping on all ports
• Precision GPIO pin timed to the AVB/1588 clock
• Full-featured forwarding and filtering control, including Access Control List (ACL) filtering
• IEEE802.1X support (Port-Based Network Access Control)
• IEEE802.1Q VLAN supportfor 128 active VLAN groups and the full range of 4096 VLAN IDs
• IEEE802.1p/Q tag insertion or removal on a per port basis and support for double-tagging
• VLAN ID tag/untag options on per port basis
• IEEE802.3x full-duplex flow control and half-duplex back pressure collision control
• IGMPv1/v2/v3 snooping for multicast packet filtering
• IPv6 multicast listener discovery (MLD) snooping
• QoS/CoS packets prioritization support: 802.1p, DiffServ-based and re-mapping of 802.1p priority field per-port basis on four priority levels
• IPv4/IPv6 QoS support
• Programmable rate limiting at ingress and egress ports
• Broadcast storm protection
• Four priority queues with dynamic packet mapping for IEEE802.1p, IPv4 DIFFSERV, IPv6 TrafficClass
• MAC filtering function to filter or forward unknown unicast, multicast and VLAN packets
• Self-address filtering for implementing ring topologies
• High-speed SPI (4-wire, up to 50MHz) interface to access all internal registers
• I2C Interface to access all registers
• MII management (MIIM, MDC/MDIO 2 wire) interface to access all PHY registers per IEEE 802.3 specification
• In-band management to access all registers via any of the five ports, strap enabled
• I/O pin strapping facility to set certain register bits from I/O pins at reset time
• Control registers configurable on-the-fly
• Port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or MII/RMII
• MIB counters for fully-compliant statistics gathering (34 MIB counters per port)
• Full-chip software power-down
• Energy detect power-down (EDPD)
• Support IEEE P802.3az Energy Efficient Ethernet (EEE)
• Wake on LAN (WoL) support

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