주문 금액이
$5000Intel EPF10K50ETC144-3
Advanced digital signal processing and control modul
EPF10K50ETC144-3 일반적인 설명
In summary, the EPF10K50ETC144-3 is a top-of-the-line FPGA that combines advanced features, high performance, and exceptional versatility. With its impressive specifications, including 10,000 logic elements, 50,000 gates, and 144 pins, this FPGA is a powerhouse that can handle a wide range of applications with ease. From digital signal processing to communication systems, the EPF10K50ETC144-3 offers the speed, flexibility, and reliability you need to bring your designs to fruition. Whether you're a seasoned FPGA expert or a newcomer to the field, this device is sure to impress with its capabilities and performance
특징
- Embedded programmable logic devices (PLDs), providing system-on-a-programmable-chip (SOPC) integration in a single device
- – Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions
- – Dual-port capability with up to 16-bit width per embedded array block (EAB)
- – Logic array for general logic functions
- High density
- – 30,000 to 200,000 typical gates (see Tables 1 and 2)
- – Up to 98,304 RAM bits (4,096 bits per EAB), all of which can be used without reducing logic capacity
- System-level features
- – MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or 5.0-V devices
- – Low power consumption
- – Bidirectional I/O performance (tSU and tCO) up to 212 MHz
- – Fully compliant with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz
- – -1 speed grade devices are compliant with PCI Local Bus Specification, Revision 2.2, for 5.0-V operation
- – Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming additional device logic
- – Fabricated on an advanced process and operate with a 2.5-V internal supply voltage
- – In-circuit reconfigurability (ICR) via external configuration devices, intelligent controller, or JTAG port
- – ClockLockTM and ClockBoostTM options for reduced clock delay/skew and clock multiplication
- – Built-in low-skew clock distribution trees
- – 100% functional testing of all devices; test vectors or scan chains are not required
- – Pull-up on I/O pins before and during configuration
- Flexible interconnect
- – FastTrack® Interconnect continuous routing structure for fast, predictable interconnect delays
- – Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions)
- – Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used by software tools and megafunctions)
- – Tri-state emulation that implements internal tri-state buses
- – Up to six global clock signals and four global clear signals
- Powerful I/O pins
- – Individual tri-state output enable control for each pin
- – Open-drain option on each I/O pin
- – Programmable output slew-rate control to reduce switching noise
- – Clamp to VCCIO user-selectable on a pin-by-pin basis
- – Supports hot-socketing
- Software design support and automatic place-and-route provided by Altera’s development systems for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800
- Flexible package options
- – Available in a variety of packages with 144 to 672 pins, including the innovative FineLine BGATM packages (see Tables 3 and 4)
- – SameFrameTM pin-out compatibility between FLEX 10KA and FLEX 10KE devices across a range of device densities and pin counts
- Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), DesignWare components, Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest, and Viewlogic
명세서
매개변수 | 값 | 매개변수 | 값 |
---|---|---|---|
Manufacturer: | Intel | Product Category: | FPGA - Field Programmable Gate Array |
RoHS: | N | Series: | EPF10K50E FLEX 10KE |
Number of Logic Elements: | 2880 LE | Adaptive Logic Modules - ALMs: | - |
Embedded Memory: | 20 kbit | Number of I/Os: | 102 I/O |
Supply Voltage - Min: | 2.5 V | Supply Voltage - Max: | 2.5 V |
Minimum Operating Temperature: | 0 C | Maximum Operating Temperature: | + 70 C |
Mounting Style: | SMD/SMT | Package / Case: | TQFP-144 |
Packaging: | Tray | Brand: | Intel / Altera |
Moisture Sensitive: | Yes | Number of Gates: | 116000 |
Number of Logic Array Blocks - LABs: | 360 LAB | Operating Supply Current: | 10 mA |
Operating Supply Voltage: | 2.5 V | Product Type: | FPGA - Field Programmable Gate Array |
Factory Pack Quantity: | 60 | Subcategory: | Programmable Logic ICs |
Total Memory: | 20480 bit | Tradename: | FLEX 10 KE |
Part # Aliases: | 970340 |
배송
배송 유형 | 배송비 | 리드타임 | |
---|---|---|---|
DHL | $20.00-$40.00 (0.50 KG) | 2-5 날 | |
페덱스 | $20.00-$40.00 (0.50 KG) | 2-5 날 | |
UPS | $20.00-$40.00 (0.50 KG) | 2-5 날 | |
TNT | $20.00-$40.00 (0.50 KG) | 2-5 날 | |
EMS | $20.00-$40.00 (0.50 KG) | 2-5 날 | |
등기 항공 우편 | $20.00-$40.00 (0.50 KG) | 2-5 날 |
처리 시간: 배송비는 지역 및 국가에 따라 다릅니다.
지불
지불 조건 | 핸드 수수료 | |
---|---|---|
은행 송금 | US$30.00의 은행 수수료를 부과합니다. | |
페이팔 | 4.0%의 서비스 수수료를 부과합니다. | |
신용 카드 | 3.5% 서비스 수수료를 부과합니다. | |
웨스턴 유니언 | charge US.00 banking fee. | |
돈 그램 | US$0.00의 은행 수수료를 부과합니다. |
보증
1. 귀하가 구입한 전자 부품에는 365일 보증이 포함되어 있으며, 우리는 제품 품질을 보장합니다.
2. 귀하가 받은 품목 중 일부가 완벽한 품질이 아닌 경우, 당사는 책임 있게 귀하의 환불 또는 교체를 준비할 것입니다. 그러나 품목은 원래 상태를 유지해야 합니다.
포장
-
단계1 :제품
-
단계2 :진공 포장
-
단계3 :정전기 방지 가방
-
단계4 :개별 포장
-
단계5 :포장 상자
-
단계6 :바코드 배송 태그
모든 제품은 정전기 방지 가방에 포장됩니다. ESD 정전기 방지 보호 장치와 함께 배송됩니다.
외부 ESD 포장 라벨은 당사 정보(부품 번호, 브랜드 및 수량)를 사용합니다.
우리는 선적 전에 모든 상품을 검사하고, 모든 제품이 양호한 상태인지 확인하고, 부품이 새로운 원본 일치 데이터시트인지 확인합니다.
모든 상품을 포장한 후 문제가 없는지 확인한 후 안전하게 포장하여 글로벌 특급으로 보내드립니다. 우수한 밀봉 무결성과 함께 탁월한 천공 및 인열 저항성을 나타냅니다.
우리는 고품질 제품, 사려 깊은 서비스 및 판매 후 보증을 제공합니다.
-
우리는 풍부한 제품을 보유하고 있으며 귀하의 다양한 요구를 충족시킬 수 있습니다.
-
최소 주문 수량은 1개부터입니다.
-
최저 국제 배송비는 $0.00부터 시작됩니다
-
모든 제품에 대해 365일 품질 보증